Typically in semiconductor device applications, numerous devices are packed into a small area of a semiconductor substrate to create an integrated circuit. Generally, these devices need to be electrically isolated from one another to avoid problems among the devices. Accordingly, electrical isolation is an important part of semiconductor device design to prevent unwanted electrical coupling between adjacent components and devices.
Shallow trench isolation (STI) is one conventional isolation method. Shallow trench isolation provides very good device-to-device isolation. A shallow trench isolation process generally includes the following steps. First, a trench is formed in a semiconductor substrate using wet or dry etching with a mask. Then, an insulating layer is deposited on the entire surface of the semiconductor substrate to fill the trench. Finally, chemical mechanical polishing (CMP) is used to planarize the insulating layer. The insulating layer remaining in the trench acts as an STI region for providing isolation among devices in the substrate. Additionally, a nitride and/or oxidation layer may be formed on the sidewalls and bottom of the trench before depositing the insulating layer.
As semiconductor devices get smaller and more complex and packing density increases, the width of the STI regions also decreases. In addition, for certain types of electronic devices, a deeper isolation trench is desired. This leads to trench isolation regions with high aspect ratios; aspect ratio refers to the height of the trench compared to its width (h:w). An aspect ratio of greater than or equal to about 3:1 is generally considered a high aspect ratio. Even when filling an isolation trench with a high-density plasma having good filling capability, voids or seams may still exist in the isolation regions. These defects cause electrical isolation between the devices to be reduced. Poor isolation can lead to short circuits and can reduce the lifetime of one or more circuits formed on a substrate.
FIG. 1 illustrates a high aspect ratio isolation trench 11 formed in a semiconductor substrate 10 in accordance with the prior art. Before forming the isolation trench 11, other layers may be deposited over the semiconductor substrate 10, for example, layers used to form gate structure, including an oxide layer 12, a polysilicon layer 14, and a nitride layer 16. After a trench 11 is formed, an insulating layer 20 is deposited over the semiconductor substrate 10 to fill the trench 11. The insulating layer 20 can be deposited using high-density plasma chemical vapor deposition (HPDCVD). Due to the high aspect ratio of the trench 11, the HPDCVD process will leave void regions 22 in the insulating layer 20. This occurs because in the process of depositing the insulating layer 20, the insulating layer 20 on the sidewalls at the top of the trench 11 grows thicker than the portion closer to the bottom of the trench 11. Therefore, the opening at the top of the trench 11 becomes closed-off before the entire volume of the trench 11 can be filled, causing the void regions 22 which diminishes the isolation properties of the filled trench 11.
One other problem that has been experienced during known trench formation is that silicon and/or polysilicon becomes oxidized when exposed to high ambient temperatures, such as when put in a furnace for steam densification. This oxidation results in undesirable changes to the properties of the oxidized material.
Accordingly, there is a need and desire for a method of forming shallow trench isolation region that achieves good isolation, but minimizing the drawbacks experienced with conventional trench isolation formation.